Advance Program
		Tuesday, April 11th
	7:30-8:30	Coffee & Registration
		location: B02 CSL
	8:30-8:45	Committee's welcome to SELSE
		Session 1:  Technology Roadmap (moderator:  Josep Torrellas)
	8:45-9:45	Panel:  Soft error scaling trends
		Nhon Quach (AMD) [slides]
		Y. Tosaka (Fujitsu)
		Eishi Ibe (Hitachi) [slides]
		David Heidel (IBM) [slides]
		Norbert Seifert (Intel) [slides]
		Vivian Zhu (TI) [slides]
	9:45-10:15	Break
		Session 2:  Mitigation Techniques 1 (chair:  Crisitan Constantinescu)
	10:15-10:45	A High-Speed Transient-Tolerant Logic Style [paper]
		Ming Zhang, Naresh Shanbhag (University of Illinois at Urbana-Champaign)
	10:45-11:15	An Accurate and Efficient Model of Electrical Masking Effect for SE in Combinatorial Logic [paper][slides]
		Feng Wang, Yuan Xie (Pennsylvania State University)
	11:15-11:45	Temperature and Voltage Scaling Effects on Electrical Masking [paper]
		Rajaraman Ramanarayanan, Ramakrishnan Krishnan, N. Vijaykrishnan, Yuan Xie, Mary J. Irwin          (Pennsylvania State University)
	11:45-12:15	Design Optimization for Robustness to Single-Event Upsets [paper]
		Quming Zhou, Mihir R. Choudhury, Kartik Mohanram (Rice University)
	12:15-1:15	Lunch
		location: 2400D Siebel Center
		Session 3:  Poster Session & Dessert (chair:  David Heidel)
	1:15-2:15	The Rosetta Experiment:  Atmospheric SER Testing in Differing Technology FPGAs [paper][poster]
		Austin Lesea, Joe Fabula (Xilinx)
		Prognostics and Health Management Techniques for Digital Electronic Devices [paper]
		Mark Baybutt, Chris Minnella, Antonio Ginart, Michael J. Roemer (Impact-Tek), Aleksey Urmanov (Sun)
		Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits [paper]
		Balaji Vaidyanathan, Yuan Xie, N. Vijaykrishnan (Pennsylvania State University), Hao Zheng                (University of South Florida)
		A Model for Soft Errors in the Subthreshold CMOS Inverter [paper][poster]
		Hua Li, Joseph Mundy, William R. Patterson, Dimitris Kazazis, Alexander Zaslavsky, R. Iris Bahar (Brown University)
		When are Multiple Gate Errors Significant in Logic Circuits? [paper]
		Smita Krishnaswamy, Igor L. Markov, John P. Hayes (University of Michigan)
		Fault tolerant DSP microprocessor for ΣΔ-modulated Signals [paper]
		Erik Schüler, Marcelo Ienczczak Ergison, Daniel Scain Farenzena, Luigi Carro                                        (Universidade Federal do Rio Grande do Sul)
		The Granularity of Soft-Error Containment in Shared-Memory Multiprocessors [paper][poster]
		Brian Gold, Jared C. Smolens, Babak Falsafi, James C. Hoe (Carnegie Mellon University)
	2:15-2:30	Break
		Session 4:  Accelerated Testing (chair:  Norbert Seifert)
		location: B02 CSL
	2:30-3:00	Neutron SER Characterization of Microprocessors
		Cristian Constantinescu (Intel)
	3:00-3:30	Proton Irradiation Analysis of SER of Single Event Upsets on IBM Power5 System
		Sertac Cakici , Pia Sanda, Kenneth Wright, Jared Day, Scott Swaney, Ethan Cannon (IBM)
	3:30-4:00	Accelerated testing of Sun's UltraSPARC processors for radiation induced soft errors
		Raymond Heald, John Moynihan, Anand Dixit, Steven Boyle, David Maxwell, Ishwar Parulkar (Sun)
	4:00-4:15	Break
	4:15-5:15	Invited talk (chair: Ravishanker K. Iyer)
		Extending and Expanding Moore's Law: Challenges and Opportunities [slides]
		Shekhar Borkar (Intel)
	5:15-5:30	Break
	5:30-6:00	Limitations of Software-Only Solutions for Soft-Error Detection [paper]
		Adam Brown, Calvin Lin (University of Texas at Austin)
	6:00-7:00	Social hour
		location: 1st floor Atrium Siebel Center
	7:00-9:00	Dinner
		Wednesday, April 12th
	7:30-8:30	Coffee
		location: B02 CSL
		Session 5:  Mitigation Techniques 2 (chair:  Naresh Shanbhag)
	8:30-9:00	Combinatorial Logic Soft Error Correction [paper]
		Subhasish Mitra (Stanford University), Ming Zhang (University of Illinois), Saad Waqas, Norbert Seifert, Balkaran Gill, Kee Sup Kim (Intel)
	9:00-9:30	Checker Backend for Soft and Timing Error Detection and Recovery [paper][slides]
		Xavier Vera, Jaume Abella, Osman Unsal, Antonio González, Oguz Ergin (Intel)
	9:30-10:00	Soft Error Resilience of Probabilistic Inference Applications [paper]
		Vicky Wong, Mark Horowitz (Stanford University)
	10:00-10:30	Break
		Session 6:  System-Level Mitigation 1 (moderator:  Babak Falsafi)
	10:30-11:30	Panel: Techniques to mitigate soft error
		Olivier Lauzeral (Iroc)
		Alan Wood (Sun)
		Patrick Meaney (IBM) [slides]
		Hisashige Ando (Fujitsu) [slides]
		John Crawford (Intel)
	11:30-12:00	Data Integrity in HP NonStop Servers [paper]
		Alan Wood, Robert Jardine, Wendy Bartlett (Hewlett Packard)
	12:00-1:15	Lunch
		location: 2400D Siebel Center
		Session 7:  System-Level Mitigation 2 (chair:  Shubu Mukherjee)
		location: B02 CSL
	1:15-1:45	Timing-Logic Derating Computation Using Event Propagation Probabilities [paper]
		Hossein Asadi, Mehdi B. Tahoori (Northeastern University)
	1:45-2:15	Symptom Based Redundant Multithreading [paper]
		Nicholas Wang (University of Illinois at Urbana-Champaign)
	2:15-2:45	Mitigation of System Effects of Soft Errors [paper]
		Aleksey Urmanov, Kenny C. Gross, Larry G. Votta (Sun)
	2:45-3:00	Break
		Session 8:  Mitigation Techniques 3 (chair:  Sarita Adve)
	3:00-3:30	Intermittent Faults in VLSI Circuits [paper][slides]
		Cristian Constantinescu (Intel)
	3:30-4:00	A First-Order Analysis of Power Overheads of Redundant Multi-threading [paper][slides]
		Niti Madan, Rajeev Balasubramonian (University of Utah)
	4:00-4:30	Processor-Level Selective Replication [paper]
		Nithin M. Nakka, Karthik Pattabiraman, Zbigniew T. Kalbarczyk, Ravishanker K. Iyer (University of Illinois at Urbana-Champaign)
	4:30-5:00	Mitigation of Transient Faults at the System Level - The TTA Approach [paper][slides]
		Hermann Kopetz (Vienna University of Technology)
	5:00-5:30	Wrap-up
		Adjourn